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KSZ8081MLXCA Datasheet - Microchip
| Manufacturer: | Microchip |
| Category: | Interface ICs |
| Case Package: | LQFP-48 |
| Description: | PHY 1CH 10Mbps/100Mbps 3.3V 48Pin LQFP Tray |
| Pictures: |
KSZ8081MLXCADatasheet PDF
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Micrel, Inc.
KSZ8081MLX
August
19, 2015
10
Revision 1.3
Pin Description (Continued)
Pin Number Pin Name Type
(2)
Pin Function
22
RXD1/
PHYAD2
Ipd/O
MII Mode: MII Receive Data Output[1]
(
3
)
.
Config. Mode: The pull-up/pull-down value is latched as PHYADDR[2] at the de-
assertion of reset. See the Strapping Options section for details.
23
RXD0/
DUPLEX
Ipu/O
MII Mode: MII Receive Data Output[0]
(
3
)
Config. Mode: The pull-up/pull-down value is latched as DUPLEX at the de-assertion
of reset. See the Strapping Options section for details.
24 GND Gnd Ground.
25 VDDIO P 3.3V, 2.5V, or 1.8V Digital V
DD
.
26 NC - No Connect. This pin is not bonded and can be left floating.
27
RXDV/
CONFIG2
Ipd/O
MII Mode: MII Receive Data Valid Output.
Config. Mode: The pull-up/pull-down value is latched as CONFIG2 at the de-assertion
of reset. See the Strapping Options section for details.
28
RXC/
B-CAST_OFF
Ipd/O
MII Mode: MII Receive Clock Output.
Config. Mode: The pull-up/pull-down value is latched as B-CAST_OFF at the de-
assertion of reset. See the Strapping Options section for details.
29
RXER/
ISO
Ipd/O
MII Mode: MII Receive Error output
Config. Mode: The pull-up/pull-down value is latched as ISOLATE at the de-assertion
of reset See the Strapping Options section for details.
30 GND Gnd Ground.
31 VDD_1.2 P
1.2V Core V
DD
(power supplied by KSZ8081MLX)
.
Decouple with 0.1µF capacitor to
ground, and join with Pin 4 by power trace or plane.
32
INTRP/
NAND_Tree#
Ipu/Opu
Interrupt Output: Programmable interrupt output.
This pin has a weak pull-up, is open drain, and requires an external 1.0kΩ pull-up
resistor.
Config. Mode: The pull-up/pull-down value is latched as NAND Tree# at the de-
assertion of reset. See the Strapping Options section for details.
33 TXC Ipd/O
MII Mode: MII Transmit Clock Output.
At the de-assertion of reset, this pin needs to latch in a pull-down value for normal
operation. If MAC side pulls this pin high, see Register 16h, Bit [15] for solution. It is
better having an external pull-down resistor to avoid MAC side pulls this pin high.
34 TXEN I MII Mode: MII Transmit Enable input.
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