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KSZ8081MLXCA Datasheet - Microchip
| Manufacturer: | Microchip |
| Category: | Interface ICs |
| Case Package: | LQFP-48 |
| Description: | PHY 1CH 10Mbps/100Mbps 3.3V 48Pin LQFP Tray |
| Pictures: |
KSZ8081MLXCADatasheet PDF
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Micrel, Inc.
KSZ8081MLX
August
19, 2015
12
Revision 1.3
Pin Description (Continued)
Pin Number Pin Name Type
(1)
Pin Function
43
LED1/
SPEED
Ipu/O
LED Output: Programmable LED1 output
Config. Mode: Latched as Speed (Register 0h, Bit [13]) at the de-assertion of reset.
See the Strapping Options section for details.
The LED1 pin is programmable using Register 1Fh Bits [5:4], and is defined as
follows:
LED Mode = [00]
Speed Pin State LED Definition
10Base-T High OFF
100Base-TX Low ON
LED Mode = [01]
Activity Pin State LED Definition
No activity High OFF
Activity Toggle Blinking
LED Mode = [10], [11]
Reserved
44 TEST/NC Ipd No Connect for normal operation, an external pull-up resistor for NAND tree testing.
45 NC - No Connect. This pin is not bonded and can be left floating.
46 NC - No Connect. This pin is not bonded and can be left floating.
47 RST# Ipu Chip Reset (active low)
48 NC - No Connect. This pin is not bonded and can be left floating.
Strapping Options
The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC MII receive input pins may drive
high/low during power-up or reset, and consequently cause the PHY strap-in pins on the MII signals to be latched to
unintended high/low states. In this case, external pull-ups (4.7kΩ) or pull-downs (1.0kΩ) should be added on these PHY
strap-in pins to ensure the intended values are strapped-in correctly.
Pin Number Pin Name Type
(5)
Pin Function
22
21
20
PHYAD2
PHYAD1
PHYAD0
Ipd/O
Ipd/O
Ipu/O
The PHY address is latched at de-assertion of reset and is configurable to any value
from 0 to 7. The default PHY address is 00001. PHY address 00000 is enabled only if
the B-CAST_OFF strapping pin is pulled high. PHY address Bits [4:3] are set to 00 by
default.
27
41
40
CONFIG2
CONFIG1
CONFIG0
Ipd/O
Ipd/O
Ipd/O
The CONFIG[2:0] strap-in pins are latched at the de-assertion of reset.
CONFIG[2:0] Mode
000 MII (default)
110 MII back-to-back
001 – 101, 111 Reserved – not used
Note:
5. Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal pull-up (see Electrical Characteristics for
value).
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