Part Datasheet Search > Interface ICs > Microchip > KSZ8081MLXCA Datasheet PDF > KSZ8081MLXCA Datasheet Pages 9/60
KSZ8081MLXCA
Price from AiPCBA
KSZ8081MLXCADatasheet PDF
Page:
of 60 Go
If the format of the manual is confusing, please download and read the original PDF file.
Micrel, Inc.
KSZ8081MLX
August
19, 2015
9
Revision 1.3
Pin Description
Pin Number Pin Name Type
(2)
Pin Function
1 GND GND Ground.
2 GND GND Ground.
3 GND GND Ground.
4 VDD_1.2 P
1.2V Core V
DD
(power supplied by KSZ8081MLX). Decouple with 2.2µF and 0.1µF
capacitors to ground, and join with Pin 31 by power trace or plane.
5 NC
No Connect. This pin is not bonded and can be left floating.
6 NC
No Connect. This pin is not bonded and can be left floating.
7 VDDA_3.3 P 3.3V Analog V
DD
.
8 NC
No Connect. This pin is not bonded and can be left floating.
9 RXM I/O
Physical Receive or Transmit Signal ( differential).
10 RXP I/O Physical Receive or Transmit Signal (+ differential).
11 TXM I/O
Physical Transmit or Receive Signal ( differential).
12 TXP I/O Physical Transmit or Receive Signal (+ differential).
13 GND Gnd Ground.
14 XO O
Crystal Feedback for 25MHz Crystal. This pin is a no connect if an oscillator or
external clock source is used.
15 XI I Crystal / Oscillator / External Clock Input (25MHz ±50ppm).
16 REXT I Set PHY Transmit Output Current. Connect a 6.49kΩ resistor to ground on this pin.
17 GND GND Ground.
18 MDIO Ipu/Opu
Management Interface (MII) Data I/O. This pin has a weak pull-up, is open-drain, and
requires an external 1.0kΩ pull-up resistor.
19 MDC Ipu
Management Interface (MII) Clock Input. This clock pin is synchronous to the MDIO
data pin.
20
RXD3/
PHYAD0
Ipu/O
MII Mode: MII Receive Data Output[3]
(
3
)
Config. Mode: The pull-up/pull-down value is latched as PHYADDR[0] at the de-
assertion of reset. See the Strapping Options section for details.
21
RXD2/
PHYAD1
Ipd/O
MII Mode: MII Receive Data Output[2]
(
3
)
Config. Mode: The pull-up/pull-down value is latched as PHYADDR[1] at the de-
assertion of reset. See the Strapping Options section for details.
Notes:
2. P = Power supply.
GND = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipu = Input with internal pull-up (see Electrical Characteristics for value).
Ipd = Input with internal pull-down (see Electrical Characteristics for value).
Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal pull-up (see Electrical Characteristics for
value).
3. MII RX Mode: The RXD[3:0] bits are synchronous with RXC. When RXDV is asserted, RXD[3:0] presents valid data to the MAC.

KSZ8081MLXCA Documents

Microchip
60 Pages / 1.28 MByte
Microchip
56 Pages / 0.97 MByte

KSZ8081 Documents

Microchip
MICROCHIP KSZ8081RNBIA-TR Ethernet Controller, 100Mbps, IEEE 802.3, 3.135V, 3.465V, QFN, 32Pins
Microchip
PHY 1CH 10Mbps/100Mbps 3.3V 24Pin QFN EP T/R
Microchip
PHY 1CH 10Mbps/100Mbps 3.3V 32Pin QFN EP T/R
Microchip
PHY 1CH 10Mbps/100Mbps 3.3V 32Pin QFN EP T/R
Microchip
Ethernet Controller, 100Mbps, IEEE 802.3, 3.135V, 3.465V, QFN, 24Pins
Microchip
PHY 1CH 10Mbps/100Mbps 3.3V 32Pin QFN EP T/R
Microchip
PHY 1CH 10Mbps/100Mbps 3.3V 24Pin QFN EP Tray
Microchip
PHY 1CH 10Mbps/100Mbps 3.3V 32Pin QFN EP Tray
Microchip
PHY 1CH 10Mbps/100Mbps 3.3V 24Pin QFN EP T/R
Microchip
PHY 1CH 10Mbps/100Mbps 3.3V 48Pin LQFP T/R
Part Datasheet PDF Search
72,405,303 Parts Datasheet PDF, Update more than 5,000 PDF files ervery day.