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Digital interfaces LIS3MDL
16/32 DocID024204 Rev 2
5 Digital interfaces
The registers embedded in the LIS3MDL may be accessed through both the I
2
C and SPI
serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire
interface mode.
The serial interfaces are mapped onto the same pads. To select/exploit the I
2
C interface, the
CS line must be tied high (i.e. connected to Vdd_IO).
5.1 I
2
C serial interface
The LIS3MDL I
2
C is a bus slave. The I
2
C is employed to write data to registers whose
content can also be read back.
The relevant I
2
C terminology is given in the table below.
There are two signals associated with the I
2
C bus: the serial clock line (SCL) and the serial
data line (SDA). The latter is a bidirectional line used for sending and receiving the data
to/from the interface. Both lines must be connected to Vdd_IO through an external pull-up
resistor. When the bus is free, both the lines are high.
The I
2
C interface is compliant with fast mode (400 kHz) I
2
C standards, as well as with
normal mode.
When the I
2
C interface is used, the SDO/SA1 pin has to be connected to Vdd_IO or GND.
Table 9. Serial interface pin description
Pin name Pin description
CS
SPI enable
I
2
C/SPI mode selection (1: SPI idle mode / I
2
C communication
enabled; 0: SPI communication mode / I
2
C disabled)
SCL
SPC
I
2
C serial clock (SCL)
SPI serial port clock (SPC)
SDA
SDI
SDO
I
2
C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
SA1
SDO
I
2
C less significant bit of the device address (SA1)
SPI serial data output (SDO)
Table 10. Serial interface pin description
Term Description
Transmitter The device which sends data to the bus
Receiver The device which receives data from the bus
Master
The device which initiates a transfer, generates clock signals and terminates a
transfer
Slave The device addressed by the master

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