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MAX1185 Datasheet - Maxim Integrated
| Manufacturer: | Maxim Integrated |
| Case Package: | TQFP-48 |
| Description: | Dual 10Bit, 20MSPS, +3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs |
| Pictures: |
MAX1185Datasheet PDF
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MAX1185
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
_______________________________________________________________________________________
9
Pin Description
PIN NAME FUNCTION
1 COM Common-Mode Voltage Input/Output. Bypass to GND with a ≥ 0.1µF capacitor.
2, 6, 11, 14, 15 V
DD
Analog Supply Voltage. Bypass each supply pin to GND with a 0.1µF capacitor. Analog
supply accepts a 2.7V to 3.6V input range.
3, 7, 10, 13, 16 GND Analog Ground
4 INA+ Channel A Positive Analog Input. For single-ended operation, connect signal source to INA+.
5 INA- Channel A Negative Analog Input. For single-ended operation, connect INA- to COM.
8 INB- Channel B Negative Analog Input. For single-ended operation, connect INB- to COM.
9 INB+ Channel B Positive Analog Input. For single-ended operation, connect signal source to INB+.
12 CLK Converter Clock Input
17 T/B
T/B selects the ADC digital output format.
High: Two’s complement.
Low: Straight offset binary.
18 SLEEP
Sleep Mode Input.
High: Deactivates the two ADCs, but leaves the reference bias circuit active.
Low: Normal operation.
19 PD
Power-Down Input.
High: Power-down mode.
Low: Normal operation.
20 OE
Output Enable Input.
High: Digital outputs disabled.
Low: Digital outputs enabled.
21–29 N.C. Do not connect.
30 A/B
A/B Data Indicator. This digital output indicates CHA data (A/B = 1) or CHB data (A/B = 0)
to be present on the output. A/B follows the external clock signal with typically 6ns delay.
31, 34 OGND Output Driver Ground
32, 33 OV
DD
Output Driver Supply Voltage. Bypass each supply pin to OGND with a 0.1µF capacitor. Output
driver supply accepts a 1.7V to 3.6V input range.
35 D0A/B
Three-State Digital Output, Bit 0 (LSB). Depending on status of A/B, output data reflects
channel A or channel B data.
36 D1A/B
Three-State Digital Output, Bit 1. Depending on status of A/B, output data reflects channel A
or channel B data.
37 D2A/B
Three-State Digital Output, Bit 2. Depending on status of A/B, output data reflects channel A
or channel B data.
38 D3A/B
Three-State Digital Output, Bit 3. Depending on status of A/B, output data reflects channel A
or channel B data.
39 D4A/B
Three-State Digital Output, Bit 4. Depending on status of A/B, output data reflects channel A
or channel B data.
40 D5A/B
Three-State Digital Output, Bit 5. Depending on status of A/B, output data reflects channel A
or channel B data.
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