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X5043S8IZ-2.7A Datasheet - Intersil
| Manufacturer: | Intersil |
| Category: | Power Monitors |
| Case Package: | SOIC-8 |
| Description: | Processor Supervisor 2.92V 2.7V to 5.5V 8Pin SOIC |
| Pictures: |
X5043S8IZ-2.7ADatasheet PDF
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1
FN8126.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas LLC
Copyright Intersil Americas LLC 2005, 2006, 2015. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X5043, X5045
4K, 512 x 8 Bit
CPU Supervisor with 4K SPI EEPROM
These devices combine four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage Supervision,
and Block Lock Protect Serial EEPROM Memory in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power-on reset
circuit which holds RESET
/RESET active for a period of
time. This allows the power supply and oscillator to stabilize
before the processor executes code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller
fails to restart a timer within a selectable time out interval,
the device activates the RESET
/RESET signal. The user
selects the interval from three preset values. Once selected,
the interval does not change, even after cycling the power.
The device’s low V
CC
detection circuitry protects the user’s
system from low voltage conditions, resetting the system
when V
CC
falls below the minimum V
CC
trip point.
RESET
/RESET is asserted until V
CC
returns to proper
operating level and stabilizes. Four industry standard V
TRIP
thresholds are available, however, Intersil’s unique circuits
allow the threshold to be reprogrammed to meet custom
requirements or to fine-tune the threshold for applications
requiring higher precision.
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s block lock protection. The
array is internally organized as 512 x 8. The device features
a Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Intersil’s proprietary Direct Write
™
cell,
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.
Features
•Low V
CC
Detection and Reset Assertion
- Four standard reset threshold voltages
4.63V, 4.38V, 2.93V, 2.63V
- Re-program low V
CC
reset threshold voltage using
special programming sequence.
- Reset signal valid to V
CC
= 1V
• Selectable Time Out Watchdog Timer
• Long Battery Life with Low Power Consumption
- <50µA max standby current, watchdog on
- <10µA max standby current, watchdog off
• 4Kbits of EEPROM–1M Write Cycle Endurance
• Save Critical Data with Block Lock
™
Memory
- Protect 1/4, 1/2, all or none of EEPROM array
• Built-in Inadvertent Write Protection
- Write enable latch
- Write protect pin
• SPI Interface - 3.3MHz Clock Rate
• Minimize Programming Time
- 16-byte page write mode
- 5ms write cycle time (typical)
• Available Packages
- 8 Ld MSOP, 8 Ld SOIC, 8 Ld PDIP
- 14 Ld TSSOP
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Communications Equipment
- Routers, Hubs, Switches
- Set Top Boxes
• Industrial Systems
- Process Control
- Intelligent Instrumentation
• Computer Systems
- Desktop Computers
- Network Servers
• Battery Powered Equipment
Data Sheet September 23, 2015
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