| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 8 Pin |
| Operating Voltage | 1.8V ~ 5.5V |
| Case/Package | SOIC-8 |
| Output Current | 22.0 mA |
| Supply Current | 1.3 mA |
| Number of Circuits | 1 Circuit |
| Number of Channels | 1 Channel |
| Number of Positions | 8 Position |
| Common Mode Rejection Ratio | 84 dB |
| Input Offset Drift | 1.50 µV/K |
| Bandwidth | 17 MHz |
| Slew Rate | 10.5 V/μs |
| Gain Bandwidth Product | 17 MHz |
| Input Offset Voltage | 26 µV |
| Input Bias Current | 0.003 pA |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Gain Bandwidth | 17 MHz |
| Minimum CMRR Range | 84 dB |
| Supply Voltage | 1.8V ~ 5.5V |
| Supply Voltage (Max) | 5.5 V |
| Supply Voltage (Min) | 2 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Size-Length | 4.9 mm |
| Size-Width | 3.9 mm |
| Size-Height | 1.45 mm |
| Operating Temperature | -40℃ ~ 125℃ |
The LMP7721MA/NOPB is a 3fA input bias current Precision Amplifier. The ultra-low input bias current is 3fA, with a specified limit of ±20fA at 25°C and ±900fA at 85°C. This is achieved with the latest patent-pending technology of input bias current cancellation amplifier circuitry. This technology also maintains the ultra-low input bias current over the entire input common-mode voltage range of the amplifier. Other outstanding features such as low voltage noise (6.5nV/√Hz), low DC-offset voltage (±150µV maximum at 25°C) and low-offset voltage temperature coefficient (-1.5 µV/°C), improve system sensitivity and accuracy in high-precision applications with a supply voltage range of 1.8 to 5.5V. The LMP7721 is part of the LMP precision amplifier family. As part of Texas Instruments" PowerWise™ products, the amplifier provides the remarkably wide-gain bandwidth product (GBW) of 17MHz while consuming only 1.3mA of current.
● 1.3mA Supply current
● 100dB DC CMRR
● 120dB DC Open loop gain
● ±26µV Off-set voltage
● Green product and no Sb/Br
●This device has limited built-in ESD protection, leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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