24LC128 Datasheet PDF

●The 24LC128-I/SN is a 16K x 8 128Kbit serial Electrically Erasable Programmable Read-only Memory (EEPROM), capable of operation across a broad voltage range (1.7 to 5.5V). It has been developed for advanced, low-power applications such as data acquisition. This device also has a page write capability of up to 64bytes of data. This device is capable of both random and sequential reads up to the 128K boundary. Functional address lines allow up to eight devices on the same bus, for up to 1Mbit address space. The 24XX128 supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The bus must be controlled by a master device which generates the Serial Clock (SCL), controls the bus access and generates the Start and Stop conditions while the 24XX128 works as a slave.

● Low-power CMOS technology

● 2-wire Serial interface, I²C™ compatible

● Cascadable up to eight devices

● Schmitt-trigger inputs for noise suppression

● Output slope control to eliminate ground bounce

● More than 1 million erase/write cycles

● 5ms Typical page write time

● Self-timed erase/write cycle

● 64-byte Page write buffer

● Hardware write-protect

●ESD sensitive device, take proper precaution while handling the device.