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74F112 Datasheet PDF

Part Series:74F112 Series
Category:Flip Flops
Description:Flip Flop JK-Type Neg-Edge 2Element 16Pin PDIP
Document:74F112PC Datasheet PDF (10 Pages)

74F112 Flip Flops Datasheet PDF

74F112 Datasheet PDF Flip Flops

7 Pages
National Semiconductor
IC JK TYPE NEG TRG DUAL 16DIP
7 Pages
Fairchild
Flip Flop JK-Type Neg-Edge 2Element 16Pin SOP-II T/R

74F112PC - Fairchild Specifications

TYPE
DESCRIPTION
Mounting Style
Through Hole
Number of Pins
16 Pin
Supply Voltage (DC)
5.00 V, 5.50 V (max)
Case/Package
DIP-16
Number of Circuits
2 Circuit
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74F112PC - Fairchild Function Overview

The 74F112 contains two independent, high-speed JK flip-flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on S#
D
or C#
D
prevents clocking and forces Q or Q# HIGH, respectively. Simultaneous LOW signals on S#
D
and C#
D
force both Q and Q# HIGH
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