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74HC109 Datasheet PDF

Part Series:74HC109 Series
Category:Flip Flops
Description:FLIP-FLOP, JK-TYPE, 75MHz, SOIC-16,
Document:74HC109D,652 Datasheet PDF (20 Pages)

74HC109 Datasheet PDF Flip Flops

19 Pages
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74HC(T)109 - Dual JK flip-flop with set and reset; positive-edge trigger DIP 16Pin
19 Pages
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Flip Flop JK# -Type Pos-Edge 2Element 16Pin SO
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IC JK TYPE POS TRG DUAL 16SOIC
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Philips
74HC/HCT109; Dual JK flip-flop with set and reset; positive-edge trigger
10 Pages
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Flip Flop JK# -Type Pos-Edge 2Element 16Pin SSOP T/R
10 Pages
Nexperia
IC JK TYPE POS TRG DUAL 16SSOP
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NXP 74HC109D, Dual, J-K Type Flip Flop, 2 → 6V, 16Pin SOIC
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Flip Flop JK# -Type Pos-Edge 2Element 16Pin SSOP Bulk
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Philips
74HC/HCT109; Dual JK flip-flop with set and reset; positive-edge trigger

74HC109D,652 - NXP Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Frequency
75 MHz
Number of Pins
16 Pin
Supply Voltage (DC)
2.00V (min)
Case/Package
SOIC-16
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74HC109D,652 - NXP Function Overview

The 74HC109D is a positive-edge trigger Dual J K\ Flip-flop with set and reset. This high-speed Si-gate CMOS device is pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The dual positive-edge triggered J K\ flip-flops with individual J, K\ inputs, clock (CP) inputs, set (SD\\) and reset (RD\\) inputs, also complementary Q and Q\ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K\ inputs control the state changes of the flip-flops as described in the mode select function table. The J and K\ inputs must be stable one set-up time prior to the low-to-high clock transition for predictable operation. The J K\ design allows operation as a D-type flip-flop by tying the J and K\ inputs together. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
J, K\ Inputs for easy D-type flip-flop
Toggle flip-flop
Standard output capability
ICC Category
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