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74HC138 Pinout Diagram

Part Series:74HC138 Series
Category:Logic ICs
Description:NXP 74HC138D Decoder / Demultiplexer, HC Family, 1 Gate, 3Input, 8 Output, 5.2mA, 2V to 6V, SOIC-16
Document:74HC138D Datasheet PDF (19 Pages)

74HC138D - NXP Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Number of Pins
16 Pin
Supply Voltage (DC)
2.00V (min)
Case/Package
SOIC-16
Number of Outputs
8 Output
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74HC138D - NXP Function Overview

The 74HC138D is a high speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC138D decoder accepts three binary weighted address inputs (A0, A1 and A3) and when enabled, provides 8 mutually exclusive active LOW outputs (Y0 to Y7). This device features three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output is HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 lines to 32 lines) decoder with just four 74HC138D ICs and one inverter. This device can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Permanently tie unused enable inputs to their appropriate active HIGH- or LOW-state.
Demultiplexing capability
Multiple input enable for easy expansion
Complies with JEDEC standard no. 7A
Ideal for memory chip select decoding
Active LOW mutually exclusive outputs
HBM EIA/JESD22-A114-F exceeds 2000V
MM EIA/JESD22-A115-A exceeds 200V
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