74HC161 Pinout Diagram

●The 74HC161D is a 4-bit presettable synchronous binary counter with asynchronous reset. This high-speed Si-gate CMOS device is pin compatible with low power Schottky TTL (LSTTL). This synchronous presettable binary counter features an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock. The outputs (Q0 to Q3) of the counters may be preset to a high or low level. A low level at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock (providing that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (CEP and CET). The look-ahead carry simplifies serial cascading of the counters.

● Synchronous counting and loading

● Two count enable inputs for n-bit cascading

● Positive-edge triggered clock

● Asynchronous reset

● Standard output capability

● Complies with JEDEC standard No. 7A