74HC164D Pinout Diagram

●The 74HC164D is a 8-bit serial-in/parallel-out Shift Register features two serial data inputs (DSA and DSB), eight parallel data outputs (Q0 to Q7). Data is entered serially through DSA or DSB and either input can be used as an active high enable for data entry through the other input. Data is shifted on the low-to-high transitions of the clock (CP) input. A low on the master reset input (MR) clears the register and forces all outputs low, independently of other inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

● CMOS Input level

● Gated serial data inputs

● Asynchronous master reset

● Complies with JEDEC standard No. 7A