74HC4051 Pinout Diagram

●The 74HC4051D is an 8 channel analogue multiplexer/demultiplexer in 16 pin SOIC package. This high speed Si-gate CMOS device is pin compatible with low power schottky TTL (LSTTL). The device is specified in compliance with JEDEC standard JESD 7A. The 74HC4051D has three digital select inputs (S0 to S2), active LOW enable input, eight independent inputs/outputs (Y0 to Y7) and common input/output (Z). When active LOW enable input is LOW, one of the eight switches is selected (low impedance ON state) by S0 to S2. With active LOW enable input HIGH, all switches are in high impedance OFF state independent of S0 to S2. The analogue inputs/outputs (Y0 to Y7 and Z) can swing between VCC as positive limit and VEE as negative limit. To operate the device as digital multiplexer/demultiplexer, VEE is connected to GND.

● Wide analogue input voltage range from -5V to 5V

● Low ON resistance of 80 ohm (typical) at VCC - VEE=4.5V

● Logic level translation to enable 5V logic to communicate with ±5V analogue signals

● Built-in break before make feature

● Features ESD protection

● Supply voltage range from 2V to 10V

● Ambient temperature range from -40°C to 125°C