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74HC595D Pinout Diagram

Part Series:74HC595D Series
Category:Shift Registers
Description:NXP 74HC595D Shift Register, HC Family, 74HC595, Serial to Parallel, Serial to Serial, 1Element, 8Bit, SOIC
Document:74HC595D Datasheet PDF (24 Pages)

74HC595D - NXP Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Frequency
100 MHz
Number of Pins
16 Pin
Supply Voltage (DC)
5.00 V
Case/Package
SOIC-16
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74HC595D - NXP Function Overview

The 74HC595D is a high speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74HC595D is an 8 stage serial shift register with a storage register and 3 state outputs. The registers have separate clocks. Data is shifted on the positive going transitions of the shift register clock input (SHCP). The data in each register is transferred to the storage register on a positive going transition of the storage register clock input (STCP). If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW.
8 bit serial input
8 bit serial or parallel output
Storage register with 3 state outputs
Shift register with direct clear
100MHz typ. shift out frequency
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