74HC73 Pinout Diagram

●The 74HC73D is a dual negative edge triggered JK Flip-flop with individual J, K, clock (nCP\\) and reset (nR\\) inputs and complementary nQ and nQ\ outputs. The J and K inputs must be stable one set-up time prior to the high-to-low clock transition for predictable operation. (nR\\) is asynchronous, when low it overrides the clock and data inputs, forcing the nQ output low and the nQ\ output high. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

● Low-power dissipation

● Complies with JEDEC standard No. 7A