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74HCT138 Datasheet PDF

Part Series:74HCT138 Series
Category:Logic ICs
Description:NXP 74HCT138D Decoder / Demultiplexer, HCT Family, 1 Gate, 3Input, 8 Output, 4mA, 4.5V to 5.5V, SOIC-16
Document:74HCT138D,653 Datasheet PDF (20 Pages)

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74HCT138D - NXP Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Number of Pins
16 Pin
Supply Voltage (DC)
4.50V (min)
Case/Package
SOIC-16
Number of Outputs
8 Output
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74HCT138D - NXP Function Overview

The 74HCT138D is a 3-to-8 inverting Decoder/Demultiplexer decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0\ to Y7\\). The device features three enable inputs (E1\, E2\ and E3). Every output will be high unless E1\ and E2\ are low and E3 is high. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder with just four 138 series ICs and one inverter. The 138 series can be used as an eight output demultiplexer by using one of the active low enable inputs as the data input and the remaining enable inputs as strobes. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Demultiplexing capability
Multiple input enable for easy expansion
Ideal for memory chip select decoding
Active low mutually exclusive outputs
TTL Input level
Complies with JEDEC standard No. 7A
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