Part Datasheet Search > Logic ICs > 74HCT4094 Datasheet PDF
Images are for reference

74HCT4094 Datasheet PDF

Part Series:74HCT4094 Series
Category:Logic ICs
Description:IC 8STAGE SHIFT/STORE BUS 16SOIC
Document:74HCT4094D,112 Datasheet PDF (24 Pages)

74HCT4094 Datasheet PDF Logic ICs

23 Pages
Nexperia
IC 8STAGE SHIFT/STORE BUS 16SOIC
23 Pages
NXP
NXP 74HCT4094D,118 Shift Register, HCT Family, 74HCT4094, Serial to Parallel, 1Element, 8Bit, SOIC, 16Pins
23 Pages
Nexperia
IC 8STAGE SHIFT/STORE BUS 16SOIC
23 Pages
Nexperia
IC 8STAGE SHIFT/STORE BUS 16SSOP
23 Pages
NXP
NXP 74HCT4094N Shift Register, 74HCT4094, Serial to Parallel, 1Element, 8Bit, DIP, 16Pins
23 Pages
NXP
Shift Register/Latch Single 8Bit Serial to Serial/Parallel 16Pin SSOP Bulk
23 Pages
NXP
Shift Register/Latch Single 8Bit Serial to Serial/Parallel 16Pin SSOP T/R
23 Pages
Nexperia
IC 8STAGE SHIFT/STORE BUS 16SSOP
23 Pages
NXP
74HC(T)4094 - 8-stage shift-and-store bus register DIP 16Pin
23 Pages
Nexperia
Shift Register/Latch Single 8Bit Serial to Serial/Parallel 16Pin SSOP
23 Pages
Philips
74HC/HCT4094; 8-stage shift-and-store bus register
22 Pages
Nexperia
IC SHIFT/STORE BUS 8STAGE 16SSOP
21 Pages
NXP
Shift Register/Latch Single 8Bit Serial to Serial/Parallel 16Pin SO T/R
21 Pages
NXP
Shift Register/Latch Single 8Bit Serial to Serial/Parallel 16Pin SSOP T/R

74HCT4094D,118 - Nexperia Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Number of Pins
16 Pin
Case/Package
SOIC-16
Number of Outputs
10 Output
Number of Circuits
1 Circuit
show more

74HCT4094D,118 - Nexperia Function Overview

The 74HCT4094D is a 8-bit serial-in/serial or parallel-out shift-and-store Bus Register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is shifted on the low-to-high transitions of the CP input. Data is available at QS1 on the low-to-high transitions of the CP input to allow cascading when clock edges are fast. The same data is available at QS2 on the next high-TO-low transition of the CP input to allow cascading when clock edges are slow. The data in the shift register is transferred to the storage register when the STR input is high. Data in the storage register appears at the outputs whenever the OE is high. A low on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs include clamp diodes.
Low-power dissipation
TTL Input level
Complies with JEDEC standard No. 7A
show more
Part Datasheet PDF Search
72,405,303 Parts Datasheet PDF, Update more than 5,000 PDF files ervery day.