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74HCT74 Datasheet PDF

Part Series:74HCT74 Series
Category:Logic ICs
Description:IC D-TYPE POS TRG DUAL 14SOIC
Document:74HCT74D,653 Datasheet PDF (30 Pages)

74HCT74 Datasheet PDF Logic ICs

22 Pages
NXP
NXP 74HCT74D,653 Flip-Flop, with Set and Reset,Complementary Output, Positive Edge, 74HCT74, D, 15ns, 59MHz, 4mA
22 Pages
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NXP 74HCT74D,652 Flip-Flop, Complementary, Differential, Positive Edge, 74HCT74, D, 45ns, 54MHz, 5.2mA, SOIC
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IC D-TYPE POS TRG DUAL 14SOIC
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NXP 74HCT74N,652 Flip-Flop, 74HCT74, D, 45ns, 54MHz, 5.2mA, DIP
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NXP 74HCT74D Flip-Flop, with Set and Reset,Complementary Output, Positive Edge, 74HCT74, D, 15ns, 59MHz, 4mA
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Flip Flop D-Type Pos-Edge 2Element 14Pin SSOP Bulk
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Philips
Dual D-type flip-flop with set and reset positive-edge trigger
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Nexperia
IC D-TYPE POS TRG DUAL 14TSSOP
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NXP
Flip Flop D-Type Pos-Edge 2Element 14Pin TSSOP Bulk
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NXP
NXP 74HCT74N Flip-Flop, 74HCT74, D, 15ns, 59MHz, 4mA, DIP
22 Pages
NXP
Flip Flop D-Type Pos-Edge 2Element 14Pin TSSOP T/R
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Nexperia
IC D-TYPE POS TRG DUAL 14SSOP
21 Pages
Philips
Dual D-type flip-flop with set and reset positive-edge trigger
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Flip Flop D-Type Pos-Edge 2Element 14Pin SO
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Dual D-type flip-flop with set and reset; positive-edge trigger

74HCT74D,653 - Nexperia Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Frequency
59 MHz
Number of Pins
14 Pin
Capacitance
3.5 pF
Case/Package
SOIC-14
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74HCT74D,653 - Nexperia Function Overview

The 74HCT74D is a dual positive edge triggered D-type Flip-flop has individual data (nD), clock (nCP), set (nSD\\) and reset (nRD\\) inputs and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the low-to-high clock transition, is stored in the flip-flop and appears at the nQ output. Schmitt-trigger action in the clock input, makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Symmetrical output impedance
Low power dissipation
High noise immunity
Balanced propagation delays
TTL Input level
Complies with JEDEC standard No. 7A
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