●Product Details
●The AD9513 features a three-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.
●There are three independent clock outputs that can be set to either LVDS or CMOS levels. These outputs operate to 800 MHz in LVDS mode and to 250 MHz in CMOS mode.
●Each output has a programmable divider that can be set to divide by a selected set of integers ranging from 1 to 32. The phase of one clock output relative to the other clock output can be set by means of a divider phase select function that serves as a coarse timing adjustment.
●One of the outputs features a delay element with three selectable full-scale delay values (1.5 ns, 5 ns, and 10 ns), each with 16 steps of fine adjustment.
●The AD9513 does not require an external controller for operation or setup. The device is programmed by means of 11 pins (S0 to S10) using 4-level logic. The programming pins are internally biased to ⅓ VS. The VREF pin provides a level of ⅔ VS. VS (3.3 V) and GND (0 V) provide the other two logic levels.
●The AD9513 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter.
●The AD9513 is available in a 32-lead LFCSP and operates from a single 3.3 V supply. The temperature range is −40°C to +85°C.
●Applications
● Low jitter, low phase noise clock distribution
● Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
● High performance wireless transceivers
● High performance instrumentation
● Broadband infrastructure
● ATE
●### Features and Benefits
● 1.6 GHz differential clock input
● 3 programmable dividers
● Divide-by in range from1 to 32
● Phase select for coarse delay adjust
● Three 800 MHz/250 MHz LVDS/CMOS clock outputs
● Additive output jitter 300 fs rms
● Time delays up to 11.6 ns
● Device configured with 4-level logic pins
● Space-saving, 32-lead LFCSP
