AD9912 Datasheet PDF

● 1 GSPS internal clock speed (up to 400 MHz output directly)

● Integrated 1 GSPS 14-bit DAC

● 48-bit frequency tuning word with 4 μHz resolution

● Differential HSTL comparator

● Flexible system clock input accepts either crystal or externalreference clock

● On-chip low noise PLL REFCLK multiplier

● 2 SpurKiller channels

● Low jitter clock doubler for frequencies up to 750 MHz

● Single-ended CMOS comparator; frequencies of

● Programmable output divider for CMOS output

● Serial I/O control

● Excellent dynamic performance

● Software controlled power-down

● Available in two 64-lead LFCSP packages

● Residual phase noise @ 250 MHz

● 10 Hz offset: -113 dBc/Hz

● 1 kHz offset: -133 dBc/Hz

● 100 kHz offset: -153 dBc/Hz

● 40 MHz offset: -161 dBc/Hz