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ADF4106 Datasheet PDF

Part Series:ADF4106 Series
Category:Clock Generators
Description:Clock Generator 20MHz to 6GHz Input 325MHz Output 16Pin TSSOP Tube
Document:ADF4106BRUZ Datasheet PDF (28 Pages)

ADF4106 Datasheet PDF Clock Generators

26 Pages
ADI
Clock Generator 20MHz to 6GHz Input 325MHz Output 16Pin TSSOP T/R
26 Pages
ADI
Clock Generator 20MHz to 6GHz Input 325MHz Output 20Pin LFCSP EP T/R
25 Pages
ADI
Clock Generator 20MHz to 6GHz Input 325MHz Output 16Pin TSSOP Tube
25 Pages
ADI
Clock Generator 20MHz to 6GHz Input 325MHz Output 20Pin LFCSP EP
25 Pages
ADI
Clock Generator 20MHz to 6GHz Input 325MHz Output 16Pin TSSOP T/R
25 Pages
ADI
Clock Generator 20MHz to 6GHz Input 325MHz Output 16Pin TSSOP T/R
25 Pages
ADI
Clock Generator 20MHz to 6GHz Input 325MHz Output 20Pin LFCSP EP T/R
25 Pages
ADI
Clock Generator 20MHz to 6GHz Input 325MHz Output 20Pin LFCSP EP T/R
24 Pages
ADI
Clock Generator 20MHz to 6GHz Input 325MHz Output 16Pin TSSOP
24 Pages
ADI
Clock Generator 20MHz to 6GHz Input 325MHz Output 20Pin LFCSP EP
24 Pages
ADI
Clock Generator 20MHz to 6GHz Input 325MHz Output 16Pin TSSOP T/R
24 Pages
ADI
Clock Generator 20MHz to 6GHz Input 325MHz Output 20Pin LFCSP EP T/R

ADF4106BRUZ - ADI Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Frequency
6 GHz
Number of Pins
16 Pin
Supply Voltage (DC)
2.70V (min)
Case/Package
TSSOP-16
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ADF4106BRUZ - ADI Function Overview

The ADF4106BRUZ is a Frequency Synthesizer that can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low noise, digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, programmable A counter and B counter and a dual-modulus prescaler (P/P + 1). The A (6-bit) counter and B (13-bit) counter, in conjunction with the dual-modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R Counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). Its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost.
Separate charge pump supply (VP) allows extended tuning voltage in 3V systems
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
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