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ATMEGA325 Datasheet PDF

Part Series:ATMEGA325 Series
Category:Microcontrollers
Description:RISC Microcontroller, 8Bit, FLASH, AVR RISC CPU, 8MHz, CMOS, PQFP64, 14 X 14MM, 1MM HEIGHT, 0.8MM PITCH, GREEN, PLASTIC, MS-026AEB, TQFP-64
Document:ATMEGA325A-AU Datasheet PDF (841 Pages)

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ATMEGA325V-8AU - ATMEL Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Frequency
8 MHz
Number of Pins
64 Pin
Supply Voltage (DC)
5.00 V, 5.50 V (max)
Operating Voltage
1.8V ~ 5.5V
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ATMEGA325V-8AU - ATMEL Function Overview

The ATmega325/3250/645/6450 provides the following features: 32/64K bytes of In-System Programmable Flash with Read-While-Write capabilities, 1/2K bytes EEPROM, 2/4K byte SRAM, 54/69 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector, an 8-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI serial port, and five software selectable power saving modes.
Features
• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
– 130 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-Chip 2-cycle Multiplier
• High Endurance Non-volatile Memory Segments
– In-System Self-programmable Flash Program Memory
• 32K Bytes (ATmega325/ATmega3250)
• 64K Bytes (ATmega645/ATmega6450)
– EEPROM
• 1K bytes (ATmega325/ATmega3250)
• 2K bytes (ATmega645/ATmega6450)
– Internal SRAM
• 2K bytes (ATmega325/ATmega3250)
• 4K bytes (ATmega645/ATmega6450)
– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C(1)
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
– Programming Lock for Software Security
• JTAG (IEEE std. 1149.1 compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
– Real Time Counter withSeparate Oscillator
–Four PWM Channels
– 8-channel, 10-bit ADC
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Universal Serial Interface with Start Condition Detector
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby
• I/O and Packages
– 53/68 Programmable I/O Lines
– 64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP
• Speed Grade:
– ATmega325V/ATmega3250V/ATmega645V/ATmega6450V:
• 0 - 4 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.7 - 5.5V
– ATmega325/3250/645/6450:
• 0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V
• Temperature range:
– -40°C to 85°C Industrial
• Ultra-Low Power Consumption
– Active Mode:
  1 MHz, 1.8V: 350 µA
  32 kHz, 1.8V: 20 µA (including Oscillator)
– Power-down Mode: 100 nA at 1.8V
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