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CD4012 Datasheet PDF

Part Series:CD4012 Series
Category:Logic Gates
Description:NAND Gate 2Element 4IN CMOS 14Pin PDIP Tube
Document:CD4012AD3 Datasheet PDF (38 Pages)

CD4012 Datasheet PDF Logic Gates

20 Pages
TI
NAND Gate 2Element 4IN CMOS 14Pin SOIC Tube
20 Pages
TI
NAND Gate 2Element 4IN CMOS 14Pin SOIC T/R
20 Pages
TI
NAND Gate 2Element 4IN CMOS 14Pin TSSOP T/R
20 Pages
TI
NAND Gate 2Element 4IN CMOS 14Pin SOP T/R
20 Pages
TI
NAND Gate 2Element 4IN CMOS 14Pin SOIC T/R
20 Pages
TI
NAND Gate 2Element 4IN CMOS 14Pin SOIC T/R
20 Pages
TI
NAND Gate 2Element 4IN CMOS 14Pin SOIC Tube
20 Pages
TI
NAND Gate 2Element 4IN CMOS 14Pin SOIC T/R
20 Pages
TI
Ic Gate Nand 2CH 4-Inp 14-Dip
19 Pages
TI
NAND Gate 2Element 4IN CMOS 14Pin CDIP Tube
19 Pages
TI
NAND Gate 2Element 4IN CMOS 14Pin TSSOP T/R
19 Pages
TI
NAND Gate 2Element 4IN CMOS 14Pin SOIC Tube
19 Pages
TI
NAND Gate 2Element 4IN CMOS 14Pin SOIC T/R
19 Pages
TI
NAND Gate 2Element 4IN CMOS 14Pin SOP T/R
19 Pages
TI
NAND Gate 2Element 4IN CMOS 14Pin SOIC T/R
19 Pages
TI
NAND Gate 2Element 4IN CMOS 14Pin TSSOP T/R

CD4012BE - TI Specifications

TYPE
DESCRIPTION
Mounting Style
Through Hole
Number of Pins
14 Pin
Supply Voltage (DC)
3.00V ~ 18.0V
Operating Voltage
3V ~ 18V
Case/Package
PDIP-14
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CD4012BE - TI Function Overview

The CD4012BE is a CMOS dual 4-input NAND Gate provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. Meets all requirements of JEDEC tentative standard no. 13B, "standard specifications for description of "B" series CMOS devices".
Propagation delay time = 60ns (typ.) at CL = 50pF, VDD = 10V
Buffered inputs and outputs
Standardized symmetrical output characteristics
Maximum input current of 1µA at 18V
100% Tested for quiescent current at 20V
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