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CY62256 Datasheet PDF

Part Series:CY62256 Series
Category:RAM Memory
Description:CYPRESS SEMICONDUCTOR CY62256NLL-55SNXI SRAM, 256Kbit, 32K x 8Bit, 4.5V to 5.5V, SOIC, 28Pins, 55ns
Document:CY62256LL-70SNC Datasheet PDF (24 Pages)

CY62256 RAM Memory Datasheet PDF

#1
CY62256LL-70SNC
1.9
Cypress Semiconductor
#4
CY62256NLL-55ZXI
3.0
Cypress Semiconductor

CY62256 Datasheet PDF RAM Memory

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SRAM Chip Async Single 3V 256Kbit 32K x 8 70ns 28Pin TSOP-I
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CY62256N Series 256KB (32K x 8) 5V 70ns Static RAM - TSOP I-28
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CY62256VN Series 256KB (32K x 8) 3V 70ns Static RAM - TSOP I-28
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CYPRESS SEMICONDUCTOR CY62256NLL-55SNXI SRAM, 256Kbit, 32K x 8Bit, 4.5V to 5.5V, SOIC, 28Pins, 55ns
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CYPRESS SEMICONDUCTOR CY62256NLL-70PXC SRAM, 256Kbit, 32K x 8Bit, 4.5V to 5.5V, DIP, 28Pins, 70ns
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CYPRESS SEMICONDUCTOR CY62256NLL-55SNXIT SRAM, 256Kbit, 32K x 8Bit, 4.5V to 5.5V, NSOIC, 28Pins, 55ns
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SRAM Chip Async Single 5V 256Kbit 32K x 8 55ns 28Pin TSOP-I T/R
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CYPRESS SEMICONDUCTOR CY62256VNLL-70SNXIT SRAM, 256Kbit, 32K x 8Bit, 2.7V to 3.6V, NSOIC, 28Pins, 70ns New
17 Pages
Cypress Semiconductor
CY62256N Series 256KB (32K x 8) 4.5 - 5.5V 55ns Static RAM - SOIC-28
17 Pages
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SRAM Chip Async Single 5V 256Kbit 32K x 8 70ns 28Pin SNC N
13 Pages
Cypress Semiconductor
SRAM Chip Async Single 5V 256Kbit 32K x 8 70ns 28Pin SNC N
13 Pages
Cypress Semiconductor
SRAM Chip Async Single 5V 256Kbit 32K x 8 70ns 28Pin PDIP
13 Pages
Cypress Semiconductor
SRAM Chip Async Single 5V 256Kbit 32K x 8 70ns 28Pin SNC N T/R
13 Pages
Cypress Semiconductor
SRAM Chip Async Single 5V 256Kbit 32K x 8 70ns 28Pin SNC N
13 Pages
Cypress Semiconductor
SRAM Chip Async Single 5V 256Kbit 32K x 8 55ns 28Pin SNC N

CY62256NLL-55SNXI - Cypress Semiconductor Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Frequency
1.00 MHz
Number of Pins
28 Pin
Supply Voltage (DC)
5.00 V, 5.50 V (max)
Operating Voltage
5 V
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CY62256NLL-55SNXI - Cypress Semiconductor Function Overview

The CY62256NLL-55SNXI is a 256kb high performance CMOS static RAM organized as 32K words by 8-bits. Easy memory expansion is provided by an active LOW chip enable and active LOW output enable and tri-state drivers. This device has an automatic power-down feature reducing the power consumption by 99.9% when deselected. An active LOW write enable signal controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins, is written into the memory location addressed by the address present on the address pins. Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remain inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high impedance state unless the chip is selected, outputs are enabled and write enable is HIGH.
Easy memory expansion with CE and OE
TTL-compatible inputs and outputs
Automatic power-down when deselected
CMOS for optimum speed/power
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