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CY7C185 Datasheet PDF

Part Series:CY7C185 Series
Category:RAM Memory
Description:CYPRESS SEMICONDUCTOR CY7C185-20PXC SRAM, 64Kbit, 8K x 8Bit, 4.5V to 5.5V, DIP, 28Pins, 20ns
Document:CY7C185-15VCT Datasheet PDF (136 Pages)

CY7C185 RAM Memory Datasheet PDF

#1
CY7C185-15VCT
0.7
Cypress Semiconductor
#2
CY7C185-25VC
1.4
Cypress Semiconductor
#3
CY7C185-25PC
1.2
Cypress Semiconductor
#4
CY7C185-35VC
1.1
Cypress Semiconductor

CY7C185 Datasheet PDF RAM Memory

35 Pages
Cypress Semiconductor
SRAM Chip Async Single 5V 64Kbit 8K x 8 20ns 28Pin CDIP
18 Pages
Cypress Semiconductor
CYPRESS SEMICONDUCTOR CY7C185-20PXC SRAM, 64Kbit, 8K x 8Bit, 4.5V to 5.5V, DIP, 28Pins, 20ns
18 Pages
Cypress Semiconductor
SRAM Chip Async Single 5V 64Kbit 8K x 8 20ns 28Pin SOJ
18 Pages
Cypress Semiconductor
SRAM Chip Async Single 5V 64Kbit 8K x 8 15ns 28Pin SOJ
18 Pages
Cypress Semiconductor
SRAM Chip Async Single 5V 64Kbit 8K x 8 15ns 28Pin SOJ
18 Pages
Cypress Semiconductor
SRAM Chip Async Single 5V 64Kbit 8K x 8 35ns 28Pin SOIC
18 Pages
Cypress Semiconductor
SRAM Chip Async Single 5V 64Kbit 8K x 8 15ns 28Pin SOJ T/R

CY7C185-20PXC - Cypress Semiconductor Specifications

TYPE
DESCRIPTION
Mounting Style
Through Hole
Number of Pins
28 Pin
Supply Voltage (DC)
5.00 V
Case/Package
DIP-28
Supply Current
110 mA
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CY7C185-20PXC - Cypress Semiconductor Function Overview

The CY7C185-20PXC is a 64kB high-performance CMOS Static Random Access Memory (SRAM) organized as 8192 words by 8-bit. Easy memory expansion is provided by an active LOW chip enable, an active HIGH chip enable and active LOW output enable and tri-state drivers. This device has an automatic power-down feature, reducing the power consumption by 70% when deselected. An active LOW write enable signal controls the writing/reading operation of the memory. When CE1 and WE inputs are both LOW and CE2 is HIGH, data on the eight data input/output pins is written into the memory location addressed by the address present on the address pins. Reading the device is accomplished by selecting the device and enabling the outputs, CE1 and OE active LOW, CE2 active HIGH, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input or output pins.
High speed - 15ns
Fast tDOE
Low active power
Low standby power
CMOS for optimum speed/power
Easy memory expansion with CE and OE
TTL-compatible inputs and outputs
Automatic power-down when deselected
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