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EP1C3T100 Datasheet PDF

Part Series:EP1C3T100 Series
Category:FPGAs
Description:Field Programmable Gate Array, 2910 CLBs, 275MHz, 2910-Cell, CMOS, PQFP100, 16 X 16MM, 0.5MM PITCH, TQFP-100
Document:EP1C3T100I7N Datasheet PDF (386 Pages)

EP1C3T100 Datasheet PDF FPGAs

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FPGA Cyclone Family 2910 Cells 405.2MHz 130nm Technology 1.5V 100Pin TQFP
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FPGA Cyclone Family 2910 Cells 320.1MHz 130nm Technology 1.5V 100Pin TQFP
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IC FPGA 65 I/O 100TQFP
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IC FPGA 65 I/O 100TQFP
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FPGA Cyclone® Family 2910 Cells 320.1MHz 130nm Technology 1.5V 100-Pin TQFP
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FPGA Cyclone® Family 2910 Cells 275.03MHz 130nm Technology 1.5V Automotive 100Pin TQFP
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Intel
IC FPGA 65 I/O 100TQFP
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Field Programmable Gate Array, 2910 CLBs, 320MHz, 2910-Cell, CMOS, PQFP100, 16 X 16 MM, 0.50 MM PITCH, TQFP-100

EP1C3T100C8N - Altera Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Frequency
275.03 MHz
Number of Pins
100 Pin
Supply Voltage (DC)
1.50 V
Case/Package
TQFP-100
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EP1C3T100C8N - Altera Function Overview

The EP1C3T100C8N is a surface mount Field Programmable Gate Array IC with PLL clock management and 2910 logic elements. The Cyclone™ field programmable gate array with features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements. It support for multiple intellectual property (IP) cores, including Altera® MegaCore® functions and Altera Megafunctions Partners Program (AMPPSM) megafunctions.
Up to 294912 RAM bits
Support for LVTTL, LVCMOS, SSTL-2 and SSTL-3 I/O standards
High-speed (640Mbps) LVDS I/O support
Low-speed (311Mbps) LVDS I/O support
311Mbps RSDS I/O support
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