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EPM3128 Datasheet PDF

Part Series:EPM3128 Series
Category:CPLDs
Description:CPLD MAX 3000A Family 2.5K Gates 128 Macro Cells 98MHz CMOS Technology 3.3V 100Pin TQFP
Document:EPM3128ATC100-10N Datasheet PDF (182 Pages)

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EPM3128ATC100-10N - Altera Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Frequency
98 MHz
Number of Pins
100 Pin
Supply Voltage (DC)
3.30 V
Case/Package
TQFP-100
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EPM3128ATC100-10N - Altera Function Overview

The EPM3128ATC100-10N is an EEPROM Complex Programmable Logic Device with 2500 usable gates and 128 macro cells. MAX 3000A CPLD is a high-performance, CMOS EEPROM-based programmable logic devices (PLDs) built on a MAX® architecture. Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance. The MAX 3000A architecture supports 100% transistor-to-transistor logic (TTL) emulation and high-density small-scale integration (SSI), medium-scale integration (MSI) and large-scale integration (LSI) logic functions.
Enhanced ISP algorithm for faster programming
Hot-socketing support
PCI compatible
Bus-friendly architecture including programmable slew-rate control
Open-drain output option
Programmable power-saving mode for a power reduction of over 50% in each macro cell
Programmable security bit for protection of proprietary designs
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