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EPM570 Datasheet PDF

Part Series:EPM570 Series
Category:CPLDs
Description:CPLD MAX II Family 440 Macro Cells 201.1MHz 0.18um Technology 2.5V/3.3V 100Pin TQFP
Document:EPM570T100C5N Datasheet PDF (298 Pages)

EPM570 Datasheet PDF CPLDs

298 Pages
Altera
CPLD MAX II Family 440 Macro Cells 201.1MHz 0.18um Technology 2.5V/3.3V 144Pin TQFP
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CPLD MAX II Family 440 Macro Cells 201.1MHz 0.18um Technology 2.5V/3.3V 100Pin TQFP
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CPLD MAX II Family 440 Macro Cells 201.1MHz 0.18um Technology 2.5V/3.3V 100Pin TFBGA
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CPLD MAX II Family 440 Macro Cells 304MHz 0.18um Technology 2.5V/3.3V 100Pin TQFP
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CPLD MAX II Family 440 Macro Cells 201.1MHz 0.18um Technology 2.5V/3.3V 256Pin FBGA
298 Pages
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CPLD MAX II Family 440 Macro Cells 304MHz 0.18um Technology 2.5V/3.3V 144Pin TQFP
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CPLD MAX II Family 440 Macro Cells 247.5MHz 0.18um Technology 2.5V/3.3V 100Pin TQFP
298 Pages
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CPLD MAX II Family 440 Macro Cells 201.1MHz 0.18um Technology 2.5V/3.3V 100Pin TFBGA
298 Pages
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CPLD MAX II Family 440 Macro Cells 201.1MHz 0.18um Technology 2.5V/3.3V 144Pin TQFP
298 Pages
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CPLD MAX II Family 440 Macro Cells 201.1MHz 0.18um Technology 2.5V/3.3V 256Pin FBGA
298 Pages
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Flash PLD, 8.7ns, 440-Cell, CMOS, PQFP100, 16 X 16MM, 0.5MM PITCH, LEAD FREE, TQFP-100
298 Pages
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CPLD MAX II Family 440 Macro Cells 304MHz 0.18um Technology 2.5V/3.3V 256Pin FBGA
298 Pages
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CPLD MAX II Family 440 Macro Cells 201.1MHz 0.18um Technology 2.5V/3.3V 100Pin TQFP
298 Pages
Altera
CPLD MAX II Family 440 Macro Cells 201.1MHz 0.18um Technology 2.5V/3.3V 256Pin FBGA
298 Pages
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CPLD MAX II Family 440 Macro Cells 201.1MHz 0.18um Technology 1.8V 100Pin TFBGA
298 Pages
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CPLD MAX II Family 440 Macro Cells 247.5MHz 0.18um Technology 2.5V/3.3V 256Pin FBGA

EPM570T100C5N - Altera Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Frequency
201.1 MHz
Number of Pins
100 Pin
Supply Voltage (DC)
3.30 V
Case/Package
TQFP-100
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EPM570T100C5N - Altera Function Overview

The EPM570T100C5N is a Flash Complex Programmable Logic Device with 570 logic elements and 440 macro cells. The MAX® II offers high I/O counts, fast performance and reliable fitting versus other CPLD architectures. Featuring MultiVolt™ core, a user flash memory (UFM) block and enhanced in-system programmability (ISP), MAX II device is designed to reduce power while providing programmable solutions for applications such as bus bridging, I/O expansion, power-on reset (POR) and sequencing control and device configuration control.
Instant-on, non-volatile architecture
Provides fast propagation delay and clock-to-output times
UFM block up to 8kb for non-volatile storage
Supports hot-socketing
ESD sensitive device, take proper precaution while handling the device.
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