HEF4027 Datasheet PDF

●The HEF4027BT is a dual JK Flip-flop features independent set-direct (SD), clear-direct (CD), clock inputs and outputs (Q, Q\\). Data is accepted when clock is low and transferred to the output on the positive-going edge of the clock. The active high asynchronous clear-direct and set-direct inputs are independent and override the J, K and clock inputs. The outputs are buffered for best system performance. Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times. It operates over a recommended VDD power supply range of 3 to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS or another input.

● Fully static operation

● Standardized symmetrical output characteristics

● Complies with JEDEC standard JESD 13-B