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LAN7500 Datasheet PDF

Part Series:LAN7500 Series
Category:Interface ICs
Description:Ethernet CTLR Single Chip 10Mbps/100Mbps/1000Mbps 1.2V/2.5V/3.3V 56Pin QFN EP Tray
Document:LAN7500-ABZJ-TR Datasheet PDF (373 Pages)

LAN7500-ABZJ - Microchip Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Number of Pins
56 Pin
Supply Voltage (DC)
3.00V (min)
Case/Package
QFN-56
Number of Positions
56 Position
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LAN7500-ABZJ - Microchip Function Overview

The LAN7500-ABZJ is a Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller contains an integrated 10/100/1000 Ethernet MAC and PHY, filtering engine, USB PHY, Hi-speed USB 2.0 device controller, TAP controller, EEPROM controller and a FIFO controller with a total of 32kB of internal packet buffering. The internal USB 2.0 device controller and USB PHY are compliant with the USB 2.0 Hi-Speed standard. The device implements control, interrupt, bulk-in and bulk-out USB endpoints. The Ethernet controller supports auto-negotiation, auto-polarity correction, HP Auto-MDIX and is compliant with the IEEE 802.3, IEEE 802.3u, IEEE 802.3ab standards. ARP and NS offload is also supported. Multiple power management features are provided, including various low power modes and "Magic Packet", "Wake On LAN" and "Link Status Change" wake events. These wake events can be programmed to initiate an USB remote wakeup.
Single chip Hi-speed USB 2.0 to 10/100/1000 Ethernet controller
10/100/1000 Ethernet MAC with full-duplex support
10/100/1000 Ethernet PHY with HP Auto-MDIX
Implements reduced power operating modes
Supports EEPROM-less
Operation for reduced BOM
NetDetach provides automatic USB attach/detach when Ethernet cable is connected/removed
Four endpoints supported
Supports vendor specific commands
Remote wakeup supported
Full-duplex flow control
Preamble generation and removal
Automatic 32-bit CRC generation and checking
9kB Jumbo frame support
Automatic payload padding and pad removal
Loop-back modes
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