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LM3S3748 Datasheet PDF

Part Series:LM3S3748 Series
Category:Microcontrollers
Description:MCU 32Bit Stellaris ARM Cortex M3 RISC 128KB Flash 2.5V/3V/3.3V 100Pin LQFP Tray
Document:LM3S3748-IQC50-A0 Datasheet PDF (882 Pages)
Updated Time: 2023/09/27 12:06:28 (UTC + 8)

LM3S3748 Microcontrollers Datasheet PDF

LM3S3748-IQC50-A0 - TI Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Number of Pins
100 Pin
Supply Voltage (DC)
2.25V (min)
Case/Package
LQFP-100
Number of Positions
100 Position
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LM3S3748-IQC50-A0 - TI Function Overview

The LM3S3748-IQC50-A0 is a Stellaris® 32-bit Microcontroller based on the ARM Cortex-M3 RISC architecture core. The device offers efficient performance and extensive integration, favourably positioning the device into applications requiring significant control-processing and connectivity capabilities. The Stellaris LM3S3000 series provides the industry"s first ARM Cortex-M3 microcontrollers with USB 2.0 full-speed on-the-go/host/device combinations. For applications requiring extreme conservation of power, the device features a battery-backed hibernation module to efficiently power down the LM3S3748 to a low-power state during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time counter (RTC), a pair of match registers, an APB interface to the system bus and dedicated non-volatile memory, the hibernation module positions the LM3S3748 microcontroller perfectly for battery applications.
32-bit ARM Cortex-M3 v7M architecture 50MHz operation
System timer, providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter
Thumb®-compatible Thumb-2-only instruction set processor core
Hardware-division and single-cycle-multiplication
Integrated nested vectored interrupt controller (NVIC)
41 Interrupts with eight priority levels
Memory protection unit (MPU)
Unaligned data access, enabling data to be efficiently packed into memory
External non-maskable interrupt signal (NMI)
ARM Thumb2 mixed 16-/32-bit instruction set
Serial wire JTAG debug port (SWJ-DP)
Three sleep modes with clock gating for low power
IEEE 1149.1-1990 compatible test access port (TAP) controller
System power control using discrete external regulator
32-bit Real-time clock (RTC)
ARM PrimeCell® 32-channel configurable µDMA controller
ARM FiRM-compliant watchdog timer
Two fully programmable 16C550-type UARTs with IrDA support
Synchronous serial interface (SSI) - master or slave operation
Two I2C modules - two transmission speeds standard (100Kbps) and fast (400Kbps)
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