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MPC5566 User Reference Manual Guide

Part Series:MPC5566 Series
Category:Microcontrollers
Description:MCU 32Bit MPC55xx e200 RISC 3072KB Flash 1.8V/2.5V/3.3V/5V 416Pin BGA Brick
Document:MPC5566MZP132 User Reference Manual Guide (1268 Pages)

MPC5566 User Reference Manual Guide Microcontrollers

1268 Pages
Freescale
MPC5566 Microcontroller Evaluation Kit 512KB RAM

MPC5566MVR132 - NXP Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Frequency
132 MHz
Number of Pins
416 Pin
Supply Voltage (DC)
1.35V (min)
Case/Package
BGA-416
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MPC5566MVR132 - NXP Function Overview

The MPC5566MVR132 is a 32-bit Microcontroller a member of the MPC5500 family of microcontrollers built on the power architecture embedded technology. This family of parts has many new features coupled with high performance CMOS technology to provide significant performance improvement over the MPC500 family. The host processor core of this device complies with the power architecture embedded category that is 100% user-mode compatible (including floating point library) with the original PowerPC instruction set. The embedded architecture enhancements improve the performance in embedded applications. The core also has additional instructions, including digital signal processing (DSP) instructions, beyond the original PowerPC instruction set. The device has two levels of memory hierarchy. The fastest accesses are to the 32kB unified cache. The next level in the hierarchy contains the 128kB on-chip internal SRAM and 3MB internal flash memory.
High-performance 132MHz 32-bit power Architecture technology e200z6 core
variable length encoding (VLE)
Memory management unit (MMU)
Signal processing extension - DSP, SIMD and floating point capabilities
2 Enhanced time processor units (eTPUs)
64-channel Enhanced direct memory access (eDMA) controller
Interrupt controller (INTC) capable of handling 339 selectable-priority interrupt sources
Frequency modulated phase-locked loop (FMPLL) to assist in EMI management
MPC500 compatible external bus interface
Nexus IEEE®-ISTO 5001 class 3+ multicore debug capabilities
40-channel Dual eQADC
4 Deserial serial peripheral interface (DSPI)
4 Controller area network (CAN) modules with 64 buffers each
2 Enhanced serial communication interface modules (eSCI)
24-channel Enhanced multiple I/O system (EMIOS) with unified channels
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