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NE3210S01 Datasheet PDF

Part Series:NE3210S01 Series
Category:JFETs
Description:Trans JFET 4V 70mA 4Pin Case S01
Document:NE3210S01-T1B Datasheet PDF (16 Pages)

NE3210S01 Datasheet PDF JFETs

15 Pages
California Eastern Laboratories
Trans JFET 4V 70mA 4Pin Case S01
15 Pages
California Eastern Laboratories
Trans JFET 4V 70mA AlGaAs 4Pin Case S01 T/R

NE3210S01 - California Eastern Laboratories Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Frequency
12 GHz
Number of Pins
4 Pin
Case/Package
SMD-1
Power Dissipation
165 mW
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NE3210S01 - California Eastern Laboratories Function Overview

DESCRIPTION
NEC"s NE3210S01 is a pseudomorphic Hetero-Junction FET that uses the junction between Si-doped AIGaAs and undoped InGaAs to create very high mobility electrons. The device features mushroom shaped TiAl gates for decreased gate resistance and improved power handling. Its excellent low noise figure and high associated gain make it suitable for DBS and commercial systems. The NE 3210S01 is housed in a low cost plastic package which is available in tape and reel.
NEC"s stringent quality assurance and test procedures assure the highest reliability and performance.
FEATURES
• SUPER LOW NOISE FIGURE:
   0.35 dB TYP at f = 12 GHz
• HIGH ASSOCIATED GAIN:
   13.5 dB TYP at f = 12 GHz
• GATE LENGTH: LG ≤ 0.20 μm
• GATE WIDTH: WG = 160 μm
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