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PALCE22V10 Datasheet PDF

Part Series:PALCE22V10 Series
Description:SPLD PAL Family 800Gates 10 Macro Cells 200MHz 5V 24Pin PDIP
Document:PALCE22V10H-15JC/4 Datasheet PDF (34 Pages)

PALCE22V10 Datasheet PDF

PALCE22V10 Datasheet PDF

34 Pages
Lattice Semiconductor
SPLD PAL Family 10 Macro Cells 38.46MHz 5V 24Pin SPDIP
34 Pages
Lattice Semiconductor
SPLD PAL Family 10 Macro Cells 38.46MHz 5V 24Pin SPDIP
34 Pages
Lattice Semiconductor
SPLD PAL Family 10 Macro Cells 125MHz 5V 24Pin SPDIP
34 Pages
Lattice Semiconductor
SPLD PAL Family 10 Macro Cells 143MHz 5V 24Pin PDIP
34 Pages
Lattice Semiconductor
SPLD PAL Family 10 Macro Cells 38.46MHz 5V 28Pin PLCC
29 Pages
Cypress Semiconductor
SPLD PAL Family 800Gates 10 Macro Cells 35.7MHz 5V 28Pin PLCC
14 Pages
Cypress Semiconductor
SPLD PAL Family 800Gates 10 Macro Cells 200MHz 5V 24Pin PDIP
13 Pages
Cypress Semiconductor
SPLD PAL Family 800Gates 10 Macro Cells 142MHz 5V 28Pin PLCC
13 Pages
Cypress Semiconductor
SPLD PAL Family 800Gates 10 Macro Cells 200MHz 5V 28Pin PLCC
13 Pages
Cypress Semiconductor
SPLD PAL Family 800Gates 10 Macro Cells 83.3MHz 5V 28Pin PLCC
13 Pages
Cypress Semiconductor
SPLD PAL Family 800Gates 10 Macro Cells 142MHz 5V 24Pin CDIP
13 Pages
Cypress Semiconductor
SPLD PAL Family 800Gates 10 Macro Cells 142MHz 5V 24Pin PDIP
13 Pages
Cypress Semiconductor
SPLD PAL Family 800Gates 10 Macro Cells 35.7MHz 5V 24Pin PDIP
13 Pages
Cypress Semiconductor
SPLD PAL Family 800Gates 10 Macro Cells 83.3MHz 5V 24Pin PDIP
13 Pages
Cypress Semiconductor
SPLD PAL Family 800Gates 10 Macro Cells 142MHz 5V 28Pin PLCC
13 Pages
Cypress Semiconductor
SPLD PAL Family 800Gates 10 Macro Cells 83.3MHz 5V 28Pin LLCC

PALCE22V10-5PC - Cypress Semiconductor Specifications

TYPE
DESCRIPTION
Mounting Style
Through Hole
Frequency
200 MHz
Number of Pins
24 Pin
Case/Package
PDIP
Supply Current
140 mA
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PALCE22V10-5PC - Cypress Semiconductor Function Overview

Functional Description
The Cypress PALCE22V10 is a CMOS Flash-erasable second-generation programmable array logic device. It is implemented with the familiar sum-of-products (AND-OR) logic structure and the programmable macrocell.
Features
• Low power
— 90 mA max. commercial (10 ns)
— 130 mA max. commercial (5 ns)
• CMOS Flash EPROM technology for electrical erasability and reprogrammability
• Variable product terms
— 2 ×(8 through 16) product terms
• User-programmable macrocell
— Output polarity control
— Individually selectable for registered or combinatorial operation
• Up to 22 input termsand 10 outputs
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