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SN74HC164 Datasheet PDF

Part Series:SN74HC164 Series
Description:HEX SCHMITT-TRIGGER INVERTERS
Document:SN74HC164N Datasheet PDF (33 Pages)

SN74HC164 Datasheet PDF

33 Pages
TI
Shift Register Single 8Bit Serial to Parallel 14Pin SOP T/R
33 Pages
TI
TEXAS INSTRUMENTS SN74HC164PW Shift Register, HC Family, 74HC164, Serial to Parallel, 1Element, 8Bit, TSSOP, 14Pins
33 Pages
TI
Shift Register Single 8Bit Serial to Parallel 14Pin TSSOP T/R
33 Pages
TI
Shift Register Single 8Bit Serial to Parallel 14Pin SOIC T/R
33 Pages
TI
Shift Register Single 8Bit Serial to Parallel 14Pin SOIC T/R
33 Pages
TI
TEXAS INSTRUMENTS SN74HC164PWT Shift Register, HC Family, 74HC164, Serial to Parallel, 1Element, 8Bit, TSSOP, 14Pins
33 Pages
TI
Shift Register, HC Family, 74HC164, Serial to Parallel, 1Element, 8Bit, DIP, 14Pins
33 Pages
TI
8Bit Parallel-Out Serial Shift Registers 14-SOIC -40℃ to 125℃
33 Pages
TI
Shift Register Single 8Bit Serial to Parallel 14Pin SOIC Tube
33 Pages
TI
Shift Register Single 8Bit Serial to Parallel 14Pin SOIC Tube
33 Pages
TI
Shift Register Single 8Bit Serial to Parallel 14Pin TSSOP Tube
33 Pages
TI
Shift Register Single 8Bit Serial to Parallel 14Pin TSSOP T/R
33 Pages
TI
HEX SCHMITT-TRIGGER INVERTERS
33 Pages
TI
8Bit Parallel-Out Serial Shift Registers 14-SO -40℃ to 125℃
33 Pages
TI
Shift Register Single 8Bit Serial to Parallel 14Pin TSSOP T/R
23 Pages
TI
Shift Register Single 8Bit Serial to Parallel 14Pin SOP Tube

SN74HC164 - TI Specifications

TYPE
DESCRIPTION
Case/Package
DIP-14
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SN74HC164 - TI Function Overview

These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up to 10 LSTTL Loads
Low Power Consumption, 80-µA Maximum ICC
Typical tpd = 20 ns
±4-mA Output Drive at 5 V
Low Input Current of 1-µA Maximum
AND-Gated (Enable/Disable) Serial Inputs
Fully Buffered Clock and Serial Inputs
Direct Clear
On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include
Testing of All Parameters.
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