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SN74LS112 Datasheet PDF

Part Series:SN74LS112 Series
Category:Flip Flops
Description:Flip Flop JK-Type Neg-Edge 2Element 16Pin PDIP Tube Flip Flop JK-Type Neg-Edge 2Element 16Pin PDIP Tube
Document:SN74LS112AN3 Datasheet PDF (38 Pages)

SN74LS112 Datasheet PDF Flip Flops

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SN74LS112AN - TI Specifications

TYPE
DESCRIPTION
Mounting Style
Through Hole
Frequency
30 MHz
Number of Pins
16 Pin
Digital Logic Level
TTL
Supply Voltage (DC)
4.75V ~ 5.25V
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SN74LS112AN - TI Function Overview

The SN74LS112AN is a dual J-K Negative-Edge-Triggered Flip-Flop with clear and preset. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. This versatile flip-flop can perform as toggle flip-flop by tying J and K high. The SN74S112A is characterized for operation from 0 to 70°C.
Fully buffered to offer maximum isolation from external disturbance
Quality and reliability
Green product and no Sb/Br
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