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TMS320C6748 Datasheet PDF

Part Series:TMS320C6748 Series
Category:Digital Signal Processors(DSPs)
Description:DSP Fixed-Point/Floating-Point 64Bit 456MHz 3648MIPS 361Pin NFBGA
Document:TMS320C6748BZWT4 Datasheet PDF (275 Pages)

TMS320C6748 Datasheet PDF Digital Signal Processors(DSPs)

275 Pages
TI
DSP Fixed-Point/Floating-Point 64Bit 456MHz 3648MIPS 361Pin NFBGA
275 Pages
TI
DSP Fixed-Point/Floating-Point 64Bit 375MHz 3000MIPS 361Pin NFBGA
275 Pages
TI
DSP Fixed-Point/Floating-Point 64Bit 456MHz 3648MIPS 361Pin NFBGA
275 Pages
TI
DSP Fixed-Point/Floating-Point 64Bit 456MHz 3648MIPS 361Pin NFBGA
275 Pages
TI
DSP Fixed-Point/Floating-Point 64Bit 375MHz 3000MIPS 361Pin NFBGA
275 Pages
TI
DSP Fixed-Point/Floating-Point 64Bit 375MHz 3000MIPS 361Pin NFBGA

TMS320C6748BZWT4 - TI Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Frequency
456 MHz
Number of Pins
361 Pin
Supply Voltage (DC)
1.25V (min)
Case/Package
LFBGA-361
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TMS320C6748BZWT4 - TI Function Overview

The TMS320C6748BZWT4 is a fixed/floating-point Digital Signal Processor provides significantly lower power than other members of the TMS320C6000™ platform of DSPs. The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user interfaces and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution. The device DSP core uses a 2-level cache-based architecture. The level 1 program cache (L1P) is a 32kB direct mapped cache and the level 1 data cache is a 32kB 2-way, set-associative cache. The level 2 program cache consists of a 256kB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache or combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional 128kB of RAM shared memory.
Dedicated 16-bit time-based counter with period and frequency control
6 Single-edge outputs, 6 dual-edge symmetric outputs or 3 dual-edge asymmetric outputs
Dead-band generation
PWM Chopping by high-frequency carrier
High-speed parallel interface to FPGAs and data converters
Data width on both channels is 8- to 16-bit inclusive
Single-data rate or dual-data rate transfers
Supports multiple interfaces with START, ENABLE and WAIT controls
Two multichannel buffered serial ports (McBSPs)
One multichannel audio serial port (McASP)
Dedicated interrupt controller
Dedicated switched central resource
Standard power-management mechanism
Two multimedia card (MMC)/secure digital (SD) card interfaces with secure data I/O (SDIO) interfaces
Hardware support for modulo loop operation
Exceptions support for error detection and program redirection
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