TPS65911 Datasheet PDF

●The TPS659113A2ZRC is an integrated Power Management IC (PMIC) dedicated to applications powered by one Li-Ion or Li-Ion polymer battery cell, 3-series Ni-MH cells or a 5V input and applications that require multiple power rails. The device provides three step-down converters, one controller for external FETs to support high current rail, eight LDOs and the device is designed to be a flexible PMIC for supporting different processors and applications. Two of the step-down converters provide power for dual processor cores and support dynamic voltage scaling by a dedicated I2C interface for optimum power savings. The third converter provides power for the I/Os and memory in the system. The device includes eight general-purpose LDOs that provide a wide range of voltage and current capabilities. Five of the LDOs support 1.0 to 3.3V with a 100mV step and three (LDO1, LDO2, LDO4) support 1.0 to 3.3V with a 50mV step. All LDOs are fully controllable by the I2C interface.

● Embedded power controller (EPC) with EEPROM programmability

● Two efficient step-down DC-DC converters for processor cores (VDD1, VDD2)

● One efficient step-down DC-DC converter for I/O power (VIO)

● One controller for external FETs (VDDCtrl)

● Dynamic voltage scaling (DVS) for processor cores

● Eight LDO voltage regulators and one RTC LDO (supply for internal RTC)

● One high-speed I2C interface for general-purpose control commands (CTL-I2C)

● Thermal shutdown protection and hot-die detection

● 32kHz Clock and reset (NRESPWRON) for system and an additional output for reset signal

● Watchdog

● Two ON and OFF LED pulse generators and one PWM generator

● Two comparators for system control, connected to VCCS pin

● JTAG and boundary scan (not accessible in functional mode)

● Real-time clock (RTC) resource with - date, time and calendar

● Real-time clock (RTC) resource with - alarm capability

● Two reset inputs - Cold reset (HDRST)

● Two reset inputs - Power initialization reset (PWRDN) for thermal reset input