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TXS0102 Datasheet PDF

Part Series:TXS0102 Series
Category:Voltage Level Translator
Description:Voltage Level Translator, 2Input, 1A, 165ns, 24Mbps, 1.65V to 5.5V, VSSOP-8
Document:TXS0102DCUR Datasheet PDF (35 Pages)

TXS0102 Datasheet PDF Voltage Level Translator

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TXS0102DCUR - TI Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Number of Pins
8 Pin
Supply Voltage (DC)
5.50V (max)
Case/Package
VSSOP-8
Output Current
50 mA
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TXS0102DCUR - TI Function Overview

The TXS0102DCUR is a two-bit non-inverting Translator IC, bidirectional voltage-level translator and can be used to establish digital switching compatibility between mixed-voltage systems. It uses two separate configurable power-supply rails, with the A ports supporting operating voltages from 1.65 to 3.6V while it tracks the VCCA supply and the B ports supporting operating voltages from 2.3 to 5.5V while it tracks the VCCB supply. This allows the support of both lower and higher logic signal levels while providing bidirectional translation capabilities between any of the 1.8, 2.5, 3.3 and 5V voltage nodes. When the output-enable (OE) input is low, all I/Os are placed in the high-impedance state, which significantly reduces the power-supply quiescent current consumption. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pull-down resistor, the minimum value of the resistor is determined by the current-sourcing capability of the driver.
No Direction-Control Signal Needed
24Mbps (Push Pull) and 2Mbps (Open Drain) Maximum Data Rates
1.65 to 3.6V on A port and 2.3 to 5.5V on B port (VCCA
VCC Isolation Feature - If Either VCC Input Is at GND, Both Ports Are in the High-impedance State
No Power-supply Sequencing Required: Either VCCA or VCCB can be Ramped First
Ioff Supports Partial-power-down Mode Operation
Latch-up Performance Exceeds 100mA Per JESD 78, Class II
Green Product, No Sb/Br
Device has limited built-in ESD protection, leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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