74AHC595PW,118 Datasheet PDF - Nexperia

The 74AHC595PW is a 8-bit CMOS serial-in/serial-out or parallel-out Shift Register with output latches. It is pin compatible with low-power Schottky TTL (LSTTL). It comes with a storage register and 3-state outputs. It has separate clocks. Data is shifted on the positive-going transitions of the shift register clock input (SHCP). The data in each register is transferred to the storage register on a positive-going transition of the storage register clock input (STCP). If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading. It is also provided with asynchronous reset (active low) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the OE\ is low.

● Balanced propagation delays

● All inputs have Schmitt-trigger action

● Inputs accept voltages higher than VCC

● CMOS Input level

● Complies with JEDEC standard No. 7A