| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Frequency | 78 MHz |
| Number of Pins | 14 Pin |
| Case/Package | SOIC-14 |
| Output Current | 25 mA |
| Number of Circuits | 2 Circuit |
| Number of Positions | 14 Position |
| Clock Speed | 85 MHz |
| Input Capacitance | 3.5 pF |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Supply Voltage | 2V ~ 6V |
| Supply Voltage (Max) | 6 V |
| Supply Voltage (Min) | 2 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Bulk |
| Size-Length | 8.75 mm |
| Size-Width | 4 mm |
| Size-Height | 1.45 mm |
| Operating Temperature | -40℃ ~ 125℃ (TA) |
The 74HC107D is a dual negative edge triggered JK Flip-flop featuring individual J and K inputs, clock (CP\\) and reset (R\\) inputs and complementary Q and Q\ outputs. The reset is an asynchronous active low input and operates independently of the clock input. The J and K inputs control the state changes of the flip-flop. The J and K inputs must be stable one set-up time prior to the high-to-low clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
● CMOS Input levels
● Complies with JEDEC standard No. 7A
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