TYPE | DESCRIPTION |
---|
Mounting Style | Surface Mount |
Frequency | 75 MHz |
Number of Pins | 16 Pin |
Supply Voltage (DC) | 2.00V (min) |
Case/Package | SOIC-16 |
Number of Circuits | 2 Circuit |
Number of Positions | 16 Position |
Clock Speed | 81 MHz |
Input Capacitance | 3.5 pF |
Operating Temperature (Max) | 125 ℃ |
Operating Temperature (Min) | -40 ℃ |
Supply Voltage | 2V ~ 6V |
Supply Voltage (Max) | 6 V |
Supply Voltage (Min) | 2 V |
TYPE | DESCRIPTION |
---|
Product Lifecycle Status | Active |
Packaging | Cut Tape (CT) |
Size-Height | 1.45 mm |
Operating Temperature | -40℃ ~ 125℃ (TA) |
The 74HC109D is a positive-edge trigger Dual J K\ Flip-flop with set and reset. This high-speed Si-gate CMOS device is pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The dual positive-edge triggered J K\ flip-flops with individual J, K\ inputs, clock (CP) inputs, set (SD\\) and reset (RD\\) inputs, also complementary Q and Q\ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K\ inputs control the state changes of the flip-flops as described in the mode select function table. The J and K\ inputs must be stable one set-up time prior to the low-to-high clock transition for predictable operation. The J K\ design allows operation as a D-type flip-flop by tying the J and K\ inputs together. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
● J, K\ Inputs for easy D-type flip-flop
● Toggle flip-flop
● Standard output capability
● ICC Category
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