74HCT138N Datasheet PDF - NXP

The 74HCT138N is a 3-to-8 inverting Decoder/Demultiplexer decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0\ to Y7\\). The device features three enable inputs (E1\, E2\ and E3). Every output will be high unless E1\ and E2\ are low and E3 is high. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder with just four 138 series ICs and one inverter. The 138 series can be used as an eight output demultiplexer by using one of the active low enable inputs as the data input and the remaining enable inputs as strobes. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

● Demultiplexing capability

● Multiple input enable for easy expansion

● Ideal for memory chip select decoding

● Active low mutually exclusive outputs

● TTL Input level

● Complies with JEDEC standard No. 7A