| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Frequency | 48.0 MHz |
| Number of Pins | 16 Pin |
| Digital Logic Level | TTL |
| Supply Voltage (DC) | 5.00 V, 6.00 V (max) |
| Case/Package | DIP |
| Number of Circuits | 8 Circuit |
| Number of Positions | 16 Position |
| Number of Bits | 8 Bit |
| Number of Gates | 1 Gate |
| Input Capacitance | 3.50 pF |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Supply Voltage (Max) | 5.5 V |
| Supply Voltage (Min) | 4.5 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Unknown |
| Packaging | Each |
| Size-Length | 19.5 mm |
| Size-Width | 6.48 mm |
| Size-Height | 4.2 mm |
The 74HCT165N is a 8-bit serial or parallel-in/serial-out Shift Register features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 and Q7\\). When the parallel load input (PL\\) is low the data from D0 to D7 is loaded into the shift register asynchronously. When PL\ is high data enters the register serially at DS. When the clock enable input (CE\\) is low data is shifted on the low-to-high transitions of the CP input. A high on CE\ will disable the CP input. Inputs include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
● Asynchronous 8-bit parallel load
● Synchronous serial input
● TTL Input level
● Complies with JEDEC standard No. 7A
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