| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Number of Pins | 20 Pin |
| Digital Logic Level | CMOS |
| Supply Voltage (DC) | 5.00 V, 5.50 V (max) |
| Case/Package | DIP |
| Output Current | 6 mA |
| Number of Circuits | 8 Circuit |
| Number of Positions | 20 Position |
| Number of Bits | 8 Bit |
| Polarity | Non-Inverting |
| Number of Gates | 8 Gate |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Supply Voltage (Max) | 5.5 V |
| Supply Voltage (Min) | 4.5 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Unknown |
| Packaging | Bulk |
The 74HCT373N is a 3-state octal D-type Transparent Latch with high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL. It is specified in compliance with JEDEC standard no-7A. It features separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all latches. The latch consists of eight D-type transparent latches with 3-state true outputs. When LE is high, data at the Dn inputs enters the latches. In this condition the latches are transparent, that is a latch output will change state each time its corresponding D input changes.
● Common 3-state output enable input
● ESD protection HBM JESD22-A114F exceeds 2000V
●ESD sensitive device, take proper precaution while handling the device.
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