| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 20 Pin |
| Supply Voltage (DC) | 4.50V (min) |
| Case/Package | TSSOP-20 |
| Number of Outputs | 8 Output |
| Output Current | 35 mA |
| Number of Positions | 20 Position |
| Number of Bits | 8 Bit |
| Number of Inputs | 8 Input |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Supply Voltage | 4.5V ~ 5.5V |
| Supply Voltage (Max) | 5.5 V |
| Supply Voltage (Min) | 4.5 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Cut Tape (CT) |
| Size-Height | 0.95 mm |
| Operating Temperature | -40℃ ~ 125℃ |
The 74HCT573PW is an octal transparent D-type Latch with 3-state outputs. It features LE and OE\ inputs. When LE is high, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is low the latches store the information that was present at the inputs a set-up time preceding the high-to-low transition of LE. A high on OE\ causes the outputs to assume a high-impedance OFF-state. Operation of the OE\ input does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
● Inputs and outputs on opposite sides of package allowing easy interface with microprocessors
● Useful as input or output port for microprocessors and microcomputers
● 3-state Non-inverting outputs for bus-oriented applications
● TTL Input level
● Complies with JEDEC standard No. 7A
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