DESCRIPTION
●The 74LVC1G74 is a high-performance, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
●The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs, and complementary Q and Q outputs.
●This device is fully specified for partial power down applications using Ioff. The Ioff circuitry disables the output, preventing damaging backflow current through the device when it is powered down.
●FEATURES
●• Wide supply voltage range from 1.65 V to 5.5 V
●• 5 V tolerant inputs for interfacing with 5 V logic
●• High noise immunity
●• Complies with JEDEC standard:
● – JESD8-7 (1.65 V to 1.95 V)
● – JESD8-5 (2.3 V to 2.7 V)
● – JESD8B/JESD36 (2.7 V to 3.6 V).
●•±24 mA output drive (VCC= 3.0 V)
●• ESD protection:
● – HBM EIA/JESD22-A114-B exceeds 2000 V
● – MM EIA/JESD22-A115-A exceeds 200 V.
●• CMOS low power consumption
●• Latch-up performance exceeds 250 mA
●• Direct interface with TTL levels
●• Inputs accept voltages up to 5 V
●• Multiple package options
●• Specified from−40°C to +85°C and−40°C to +125°C.
