| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Frequency | 500 MHz |
| Number of Pins | 5 Pin |
| Supply Voltage (DC) | 1.65V (min) |
| Case/Package | SC-70-5 |
| Output Current | 50 mA |
| Number of Circuits | 1 Circuit |
| Number of Positions | 5 Position |
| Clock Speed | 500 MHz |
| Number of Bits | 1 Bit |
| Input Capacitance | 5 pF |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Supply Voltage | 1.65V ~ 5.5V |
| Supply Voltage (Max) | 5.5 V |
| Supply Voltage (Min) | 1.65 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tape & Reel (TR) |
| Size-Width | 1.35 mm |
| Size-Height | 1 mm |
| Operating Temperature | -40℃ ~ 125℃ (TA) |
The 74LVC1G79GW is a single positive-edge triggered D-type Flip-flop features that the information on the data input is transferred to the Q-output on the low-to-high transition of the clock pulse. The D-input must be stable one set-up time prior to the low-to-high clock transition for predictable operation. Inputs can be driven from either 3.3 or 5V devices. This feature allows the use of this device in a mixed 3.3 and 5V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
● High noise immunity
● CMOS low power consumption
● Latch-up performance exceeds 250mA
● Direct interface with TTL levels
● ±24mA Output drive current
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