| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 20 Pin |
| Supply Voltage (DC) | 1.65V (min) |
| Case/Package | TSSOP-20 |
| Number of Outputs | 8 Output |
| Output Current | 50 mA |
| Number of Positions | 20 Position |
| Number of Bits | 8 Bit |
| Number of Inputs | 8 Input |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Supply Voltage | 1.2V ~ 3.6V |
| Supply Voltage (Max) | 3.6 V |
| Supply Voltage (Min) | 1.65 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tape & Reel (TR) |
| Size-Height | 0.95 mm |
| Operating Temperature | -40℃ ~ 125℃ |
The 74LVC573APW is an octal transparent D Latch with 5V tolerant inputs/outputs. It features separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enables input (pin LE) and an output enable input (pin OE\\) is common to all internal latches. When pin LE is high, data at the D-inputs (pins D0 to D7) enters the latches. In this condition, the latch is transparent, that is, a latch output will change each time its corresponding D-input changes. When pin LE is low, the latch stores the information that was present at the D-inputs one set-up time preceding the high-to-low transition of pin LE. When pin OE\ is low, the contents of the eight latches are available at the Q-outputs (pins Q0 to Q7). When pin OE\ is high, the outputs go to the high-impedance OFF-state. Operation of input pin OE does not affect the state of the latches. Inputs can be driven from either 3.3 or 5V devices.
● CMOS low power consumption
● Direct interface with TTL levels
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